Reducing DC Link Voltage Unbalance in a Fault-Tolerant Inverter
- Autori: Boscaino, V.; DI TOMMASO, A.; Genduso, F.; Miceli, R.
- Anno di pubblicazione: 2014
- Tipologia: Proceedings (TIPOLOGIA NON ATTIVA)
- OA Link: http://hdl.handle.net/10447/98235
Today, continuous working of power inverter drives is mandatory for several applications. Damages to materials, machines or even risks to human life have to be absolutely avoided. In the literature, fault-tolerant algorithms and architectures to achieve a successful fault handling are investigated. Researchers aim at reducing the number and cost of additional components, improving at the same time the inverter performances under postfault conditions. Cost, post-fault power derating and increasing distortion are usually conflicting requirements. In this paper, a fault-tolerant three phase inverter is presented. A reconfigurable architecture and a novel fault-tolerant algorithm is designed to reduce DC Link Voltages unbalance. The system is modeled in PSIM-MATLAB/Simulink environment. The power stage model is implemented in PSIM environment. The fault-tolerant algorithm is implemented in MATLAB-Simulink environment. The SimCoupler module is used to perform co-simulation of the entire model. Simulation results are shown to test performances of the proposed algorithm.