How far will Silicon nanocrystals push the scaling limits of NVMs technologies?
- Authors: De Salvo, B.; Gerardi, C.; Lombardo, S.; Baron, T.; Perniola, L.; Mariolle, D.; Mur, P.; Toffoli, A.; Gely, M.; Semeria, M.; Deleonibus, S.; Ammendola, G.; Ancarani, V.; Melanotte, M.; Bez, R.; Baldi, L.; Corso, D.; Crupi, I.; Puglisi, R.; Nicotra, G.; Rimini, E.; Mazen, F.; Ghibaudo, G.; Pananakakis, G.; Monzio Compagnoni, C.; Ielmini, D.; Lacaita, A.; Spinelli, A.; Wan, Y.; Van der Jeugd, K.
- Publication year: 2003
- Type: eedings
- OA Link: http://hdl.handle.net/10447/179606
Abstract
For the first time, memory devices with optimized high density (2E12#/cm2) LPCVD Si nanocrystals have been reproducibly achieved and studied on extensive statistical basis (from single cell up to 1Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND Flash at least to the 35nm and 65nm nodes, respectively.